JPH0151236B2 - - Google Patents

Info

Publication number
JPH0151236B2
JPH0151236B2 JP57099083A JP9908382A JPH0151236B2 JP H0151236 B2 JPH0151236 B2 JP H0151236B2 JP 57099083 A JP57099083 A JP 57099083A JP 9908382 A JP9908382 A JP 9908382A JP H0151236 B2 JPH0151236 B2 JP H0151236B2
Authority
JP
Japan
Prior art keywords
data
control
memory
processing unit
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57099083A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59291A (ja
Inventor
Masatoshi Abe
Hiroshi Ozawa
Akio Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Dai Ichi Communications Software Ltd
Fujitsu Ltd
Original Assignee
Fujitsu Dai Ichi Communications Software Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Dai Ichi Communications Software Ltd, Fujitsu Ltd filed Critical Fujitsu Dai Ichi Communications Software Ltd
Priority to JP9908382A priority Critical patent/JPS59291A/ja
Publication of JPS59291A publication Critical patent/JPS59291A/ja
Publication of JPH0151236B2 publication Critical patent/JPH0151236B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
JP9908382A 1982-06-09 1982-06-09 メモリクリア方式 Granted JPS59291A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9908382A JPS59291A (ja) 1982-06-09 1982-06-09 メモリクリア方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9908382A JPS59291A (ja) 1982-06-09 1982-06-09 メモリクリア方式

Publications (2)

Publication Number Publication Date
JPS59291A JPS59291A (ja) 1984-01-05
JPH0151236B2 true JPH0151236B2 (en]) 1989-11-02

Family

ID=14238009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9908382A Granted JPS59291A (ja) 1982-06-09 1982-06-09 メモリクリア方式

Country Status (1)

Country Link
JP (1) JPS59291A (en])

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62208794A (ja) * 1986-03-06 1987-09-14 Fujitsu Ltd プロセツサ間デ−タ転送方式
JPH084869B2 (ja) * 1993-04-05 1996-01-24 豊田通商株式会社 金属製角形超薄肉背高ケースの製造方法とそのための金型

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55149556A (en) * 1979-05-10 1980-11-20 Nec Corp Failure transfer unit
JPS5741062A (en) * 1980-08-26 1982-03-06 Nec Corp Information transfer system

Also Published As

Publication number Publication date
JPS59291A (ja) 1984-01-05

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